The present invention relates to a method of manufacturing a semiconductor device wherein a multilayered structure is etched to form a pattern therein. The present invention is particularly applicable to methods for monitoring the etching of a polysilicon layer in a semiconductor device.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor devices require smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, problems are generated that require resolution in terms of new methods of fabrication or new arrangements or both.
In general, semiconductor devices comprise a substrate and elements such as transistors and/or memory cells thereon. Metal-oxide-semiconductor (MOS) type devices are typical of modem integrated circuits and typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region between the source/drain regions. A gate arrangement is then formed by depositing a thin gate oxide above the channel region followed by the deposition of a composite layer on the gate oxide to function as a gate electrode. The composite layer typically comprises one or more conductive layers which typically includes a layer of polysilicon.
Of particular importance in memory and logic devices is the formation and dimensional control of the gate electrode. Gate dimensions are critical since the gate electrode of the device controls the flow of electrons and is vital to proper device operation. As discussed above, a gate structure is formed by depositing a conductive layer at a uniform thickness, which is then typically followed by the deposition of an antireflective film on the conductive layer. A patterned photoresist or mask is then formed by depositing and patterning a photoresist material on the antireflective film followed by etching through the film and multiple layers to ultimately form the desired gate structure.
The basic photolithography system conventionally employed in forming these features consists of a light source, a stencil or photomask containing the pattern to be transferred to the semiconductor substrate, a collection of lenses, and a means for aligning existing patterns on the substrate with patterns on the mask. The resolution of an optical projection system such as a photolithographic system is limited in practice and can range from 0.8 down to 0.3 micron for standard exposure systems. The highest resolution in optical lithography is currently achieved with deep ultra violet (DUV) systems operating at 248 nm wavelengths but mid ultra violet (MUV) systems with a wavelength of 356 nm are also in widespread use.
The limits of photolithography are now being challenged, however, by the manufacture of high-performance logic and memory technologies. These technologies are entering development cycles with immediate requirements for sub-quarter micron, or less, printed gate lengths and tight dimensional control on the gate structures across large chip areas.
Since fabrication of a gate arrangement requires the further step of etching through the patterned photoresist, the gate arrangement is approximately limited to the resolution obtained in the photolithographic process. Resolving narrower line widths than those formed by the photolithographic process requires additionally demanding processing steps. Moreover, resolving the spaces between photoresist lines and other small areas using conventional lithographic techniques is considerably more difficult.
A common technique that compensates for the inherent deficiencies of optical photolithography to produce finer line widths is accomplished by etching the sidewalls of a formed photoresist mask prior to etching through the photoresist mask to form the gate structure. This trimming process is achieved by adjusting the etching parameters to etch the sidewalls of a photoresist mask to reduce the width of the elements defined by the photoresist mask. In accordance with conventional techniques, a patterned photoresist layer is placed in a plasma etching environment for a fixed period of time under prescribed etching conditions to etch the sidewalls of the photoresist mask thereby reducing the line width of the patterned photoresist.
The time and etching parameters necessary to achieve the appropriate width reduction is empirically determined by adjusting various etch parameters and, in a separate step, measuring the resulting line widths, as by scanning electron microscopy. The procedure is repeated until the appropriate time and parameters have been determined for a given pattern density. Then, batches of semiconductor substrates with an overlaying photoresist mask are repeatedly processed with the empirically determined parameters. Conventional trimming processes, however, fail to account for variations during the individual wafer processes, such as fluctuating chamber conditions, process parameter fluctuations etc. or for a changed pattern density on the substrate to be etched.
Systems for determining the completion of an etching process through an underlayer are known (see, e.g. S. Wolf and R. N. Taulber xe2x80x9cSilicon Processing for the VLSI Eraxe2x80x9d, vol. 1, Latice Press 1986, pp. 447-458 and pp. 565-567). For example, laser interferometry and optical emission spectroscopy have been used to measure the time for complete etching through an underlayer, particularly complete etching through an underlying silicon oxide, polysilicon or aluminum layer. However, it is believed that the art has not recognized a method of determining the completion of an etch step by measuring or monitoring the actual lateral, e.g. width, dimensions of a photoresist element during etching.
As the gate electrode critical dimensions shrink, process variations become increasingly intolerable. Thus, there is a need for a method of determining the dimensions of a line width during lateral processing of a photoresist mask. Further, it would be highly advantageous to develop a process capable of controlling the line width dimensions, to minimize processing variations and to precisely control gate electrode dimensions during photoresist mask etching.
An advantage of the present invention is a method of laterally processing a photoresist mask having a plurality of elements by accurately etching and monitoring the width of the elements of the photoresist mask.
Another advantage of the present invention is a method for etching a feature in a semiconductor substrate by accurately controlling the lateral dimensions of an overlaying photoresist mask.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of laterally processing a photoresist mask on a substrate, which method comprises: depositing a layer of photoresist material on the substrate; patterning the photoresist layer to form a photoresist mask having at least one element with a first prescribed width; laterally processing the photoresist mask having the element to a second prescribed width in a plasma chamber having an etchant mixture; detecting a change in the emission spectrum of at least one specie in the plasma while simultaneously laterally processing the photoresist mask; and stopping the lateral processing when the detected change in the emission spectrum of the specie corresponds to the second width.
By monitoring the emission spectrum, particularly the intensity of a selected plasma specie formed in the plasma, for changes in the plasma emission spectrum of the selected plasma specie, the present invention advantageously provides an in-situ method for precisely determining the optimum time for complete lateral processing of the photoresist mask element.
Another aspect of the present invention is a method of etching a feature on a semiconductor substrate. The method comprises: forming a dielectric layer on the semiconductor substrate; forming a conductive layer on the dielectric layer; forming a photoresist mask having at least one element having a first prescribed width on the conductive layer; laterally processing the photoresist mask having the element to a second prescribed width in a plasma chamber having an etchant mixture; detecting a change in the emission spectrum of at least one specie in the plasma while simultaneously laterally processing the photoresist mask; stopping the lateral processing when the detected change in the emission spectrum of the specie corresponds to the second width; and etching through the photoresist mask having the element with the second width to the underlying layers to form the feature.
Additional advantages of the present invention will become readily apparent to those having ordinary skill in the art from the following detailed description, wherein the embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.